Exemplary embodiments of the present invention relate to a semiconductor memory device, and more particularly, to an internal negative voltage generation device of a semiconductor memory device.
In general, a semiconductor memory device includes a large number of memory cells as basic units, which form a matrix-shaped array. Each memory cell of a Dynamic Random Access Memory (DRAM), which is a representative semiconductor memory device, includes one NMOS transistor and one capacitor. In the memory cell of a DRAM, a loss of data stored in the memory cell occurs due to a variety of leakage factors. The leakage factors may include off leakage which causes a data loss even when a memory cell is not selected.
To prevent such a data loss caused by the leakage, a DRAM performs a refresh operation to amplify and restore data at set time intervals.
To reduce the off leakage of the memory cell, the threshold voltage of a memory cell transistor may be increased. In this case, however, a time period required for storing data in the memory cell may increase.
Accordingly, a negative word line scheme has been adopted, which may improve a refresh characteristic without increasing a time period required for storing data in a memory cell.
In the negative word line scheme, the level of a voltage supplied to a word line in a precharge state in which a word line is not selected is maintained at a negative level lower than that of a ground voltage VSS. Therefore, it is possible to regulate the off leakage using a gate-source voltage relationship without increasing the threshold voltage of a memory cell transistor.
FIG. 1 illustrates a conventional regulator-type internal negative voltage generation device.
Referring to FIG. 1, the negative interval voltage generation device 100 includes a back-bias voltage generation block 110 and a negative word line driving voltage generation block 120. The back-bias voltage generation block 110 is configured to generate a back-bias voltage VBB which is lower than a ground voltage. The negative word line driving voltage generation block 120 is configured to generate a negative word line driving voltage VBBW having a voltage level between the ground voltage and the back-bias voltage VBB through a regulating operation.
The back-bias voltage generation block 110 includes a voltage detection unit 112, an oscillating unit 114, and a pumping unit 116. The voltage detection unit 112 is configured to compare a first reference voltage VR_VBB with a fed-back voltage of the back-bias voltage VBB and to output a detection signal DET as the comparison result. The first reference voltage VR_VBB corresponds to a target voltage level of the back-bias voltage VBB. The oscillating unit 114 is configured to generate and output an oscillation signal OSC at a corresponding frequency in response to the detection signal DET outputted by the voltage detection unit 112. The pumping unit 116 is configured to perform a pumping operation in response to the oscillation signal OSC outputted from the oscillating unit 114 and to generate the back-bias voltage VBB in accordance with the pumping operation. The pumping unit 116 may be implemented as a negative charge pump.
The negative word line driving voltage generation block 120 includes a voltage comparison unit 122 and a driving unit 124. The voltage comparison unit 122 is configured to compare a second reference voltage VR_VBBW and a fed-back voltage of the negative word line driving voltage VBBW, and to generate and output a driving control signal DRV corresponding to a comparison result. The second reference voltage VR_VBBW corresponds to a target voltage level of the negative word line driving voltage VBBW. The driving block 124 is configured to generate a negative word line driving voltage VBBW in response to the driving control signal DRV outputted by the voltage comparison unit 122. The driving unit 124 is implemented as an NMOS transistor coupled between a back-bias voltage (VBB) terminal and a negative word line driving voltage (VBBW) terminal, the NMOS transistor receiving the driving control signal DRV outputted by the voltage comparison unit 122 through a gate thereof.
The regulator-type internal negative voltage generation device 100 configured in such a manner has the following problem.
The negative word line driving voltage VBBW generated by the negative word line generation device 110 is supplied to an NMOS transistor of a memory cell through a word line driver. The word line driver and the NMOS transistor of the memory cell are not illustrated in the drawing. The negative word line driving voltage VBBW is varied by the consumption of dynamic power when the NMOS transistor of the memory cell is turned on/off by the word line driver. In other words, when the output signal of the word line driver changes its logic level, that is, when the output signal is ‘activated’, the negative word line driving voltage VBBW is changed. In this case, the changing negative word line driving voltage VBBW is supplied to a word line which does not change its logic level, that is, which is ‘deactivated’. As a result, the data maintenance ability of the corresponding memory cell is degraded.
Furthermore, a plurality of comparators and a plurality of drivers may be distributed and arranged to generate a stable negative word line driving voltage VBBW. Since the plurality of comparators may have different characteristics, this may also act as a factor which causes variations in the negative word line driving voltage VBBW.